The Nano Thin Film Deposition session focuses on cutting-edge research and innovative insights related to thin film materials, processing, and device manufacturing for emerging memory and logic semiconductor applications. With the semiconductor market continuously advancing toward higher density and greater performance, there is a growing demand for sophisticated nanoscale thin film processing to facilitate the integration of alternative materials and complex three-dimensional (3D) device structures. Therefore, the primary objective of this session is to introduce the latest research outcomes on advanced thin film technologies, surface science, and inorganic/organic chemistry for the development of new materials and their applications in devices. Additionally, theoretical simulations of thin film deposition reactions and the development of chemical precursors will be discussed in this session. This symposium serves as a platform for researchers from diverse fields, including materials science, surface science, inorganic chemistry, condensed matter physics, electrical engineering, and quantum information science, to exchange the latest research findings and pioneer new frontiers in thin film deposition research.

• Advanced thin films for semiconductor applications
• Chemical and physical deposition techniques for semiconductors
• Atomic layer deposition (ALD) and its applications in semiconductors
• Area-selective deposition methods for next-generation semiconductors
• Precursor development for CVD and ALD processes
• Emerging applications of nanoscale thin films in semiconductors
• Modeling, simulation, and theoretical studies of nano thin films
• Other topics related to semiconductor thin films

The continuous advancements in semiconductor manufacturing, driven by the increasing complexity of device architectures and the introduction of emerging materials, highlight the critical importance of refined Chemical Mechanical Planarization (CMP) and Cleaning processes. As the industry embraces next-generation IC production, including 3D device integration and advanced packaging, it is essential to employ sophisticated CMP techniques and optimized cleaning solutions to maintain the highest standards of device quality and minimize defects.

This session will delve into the latest innovations in dielectric and metal CMP processes, along with cutting-edge approaches to CMP for advanced packaging. Discussions will also encompass CMP consumables and equipment, as well as the crucial role of post-CMP cleaning processes in preserving wafer integrity. Furthermore, the session will explore the development of wet etchant materials and high selectivity technologies, which are essential for precise material removal.

In addition, we will examine the synthesis and surface modification of nanoparticles, alongside the foundational principles, modeling, and simulation methods that underpin effective CMP and cleaning processes. Attention will also be given to emerging and alternative CMP and cleaning technologies, as well as the pursuit of sustainable materials and processes. The goal of this session is to provide a comprehensive understanding of the latest advancements in CMP and cleaning, emphasizing how these technologies address the evolving challenges of modern semiconductor manufacturing with a focus on precision, sustainability, and performance.

• Dielectric and metal CMP processes
• Advanced packaging CMP
• CMP consumables and equipment
• Post-CMP cleaning solutions and processes
• Wet etchant materials and high selectivity technologies
• Synthesis and surface modification of nanoparticles
• CMP/ Cleaning fundamentals, modeling and simulation
• Emerging and alternative CMP/ Cleaning technologies
• Sustainable CMP/ Cleaning materials and process

Etching processes in semiconductor device fabrication are becoming increasingly challenging as critical dimensions shrink to the nanometer and atomic scale, and device architectures transition from two-dimensional (2D) to three-dimensional (3D) structures. Next-generation etch technologies must meet demanding requirements such as low-damage etching, high selectivity, and the ability to achieve high aspect ratios on both 2D and 3D device structure. This session will cover a broad range of advanced etch technologies, including atomic layer etching (ALE), cyclic etching, pulsed plasma etching, low-temperature and cryogenic etching, and sustainable etching using low global warming potential (GWP) materials. Researchers and engineers working on etching processes for semiconductor and display materials are warmly invited to participate in this session and are encouraged to share and present their work.

• Atomic Layer Etching (ALE) Techniques
• Low-Temperature and Cryogenic Etching Processes
• Advanced Plasma Etching Technologies
• Plasma Diagnostics and Process Monitoring
• Plasma Source Development for Etching Applications

It will be highlighted the continued increasing maturity and adoption of EUV lithography in high volume manufacturing as well as a glimpse of the potential of the recently released 0.55-NA scanne because more significant breakthroughs are needed to support the high-volume manufacturing introduction of 0.55-NA EUV lithography. In particular, the topics of high-NA resists and next generation masks remain a significant concern. Specifically, advancements and possible solutions are needed for patterning stochastics in resist materials/processes (which can lead to roughness and failures thereby affecting yield), the extension of EUV mask infrastructure and technology (including alternative mask absorber developments and phase shift masks), and mask defectivity (including alternative pellicle developments). Another topic that has of late become a focus is the possibility of full-field exposures at 0.55-NA through new solutions, e.g. the application of larger masks (6 x 12inch). All aspects of EUV lithography are solicited with special interest on topics addressing the primary concerns called out above.
This symposium covers a broad spectrum of lithography and patterning topics, attracting participants from diverse backgrounds to share and learn about state-of-the-art lithographic tools, resists, metrology, materials, design, process integration, and novel approaches. The symposium also fosters provocative discussions and seminars to address current issues in the field, such as extending current methods, exploring alternative approaches, and identifying new ways to complement existing technologies.

• Lithography tools, including sources and optics
• Mask metrology, inspection, and imaging, Mask lifetime, protection, and pellicles, Mask architecture and alternative materials
• Resist and underlayer materials/process, Process control and stochastics, Patterning and process enhancement
• EUV lithography extendibility, Stitching for half-field patterning with 0.55-NA NA
• Nano Fabrication for next generation optical devices: Nanoprinting for optical metasurfaces, printable nanolasers
• Advanced Metrology and Inspection: optical inspection, interference microscopy, advanced process control, overlay metrology, computational metrology
• Alternative Lithography: 3D Patterning, Imprinting, Self-assemble, non-conventional lithography
• Applications and Related Emerging Topics

Advanced Packaging Technology: A Key Technology in AI Semiconductor Modules
 
Post Fabrication Technology and System Packaging is gaining attention as a core technology for manufacturing AI semiconductor modules. Along with AI memory such as HBM (High Bandwidth Memory), GPUs and HBMs are being introduced to the market through 2.5D packaging. The current advancements in AI technology have been made possible by these cutting-edge packaging technologies, making them highly significant not only industrially and economically but also socially.

AI is being applied in various fields, including data centers, smartphones, and mobility, with the volume of absolute data increasing exponentially. Consequently, continuous and innovative technological developments in advanced packaging are essential.

The Post Fabrication Technology and System Packaging division aims to examine technological development trends in this field, academically and industrially, to anticipate and prepare for the future of leading-edge technologies.

• Topics related to advanced packaging: Electrical, optical, mechanical, thermal design, analysis, and verification
• Topics related to advanced packaging: Materials, components, and processes
• Topics related to 2.1D, 2.3D, 2.5D, 3D, and embedding technologies
• Topics related to inspection and testing
• Topics related to reliability

The advancement in IC manufacturing has introduced novel fabrication techniques such as three-dimensional stacked integrated circuit (3DS-IC) fabrication and emerging devices including 3D V-NAND flash memory, 3D DRAM, PIM, ferroelectrics, and new types of transistors. However, these new techniques have presented challenges for both in-line and ex-situ metrology and characterization.
The production of 3DS-ICs requires complex processes such as high-aspect ratio through-silicon vias (TSVs), thin wafer handling and processing, wafer thinning, and bonding of thin wafers with complex patterned surfaces, each of which pose unique metrology challenges. Additionally, 3D gate stack integration creates atomic scale defect control issues that were not previously encountered in planar FETs.

Moreover, emerging devices like ferroelectric FETs, TFETs, and NCFETs, developed for PIM and steep switching MOSFETs, demand frontier metrology for ultrathin materials and interfaces. Effective process monitoring metrology and nano-scale particles and contamination control are also critical to achieve high device-to-device and lot-to-lot uniformity and target device properties.
Therefore, the purpose of this symposium is to introduce the latest research results on various nano-scale analysis and process modeling on thin films, interfaces, particles, defects, and contaminations in advanced IC manufacturing including but not limited to 3D device integration and emerging devices and materials as well as process diagnosis and monitoring metrology.

• Topics related with advanced metrology and inspection
• Topics related with Process diagnostics and control
• Topics related with yield management
• Topics related with physical and chemical analysis of wafer processing
• Topics related with physical and chemical analysis of nano-/micro-scale particles and defects
• Topics related with analysis of contaminations on organic and inorganic materials
• Topics related with MI & process diagnosis for current and next generation semiconductor (Si, SiGe, ferroelectric, 2D materials, etc)

In this session, a wide range of topics related to the technological value-chain of power devices based on advanced Si and wide bandgap semiconductor will be discussed. Regarding materials for power devices, presentation will cover the substrate and epitaxial layer growth of SiC, GaN, Ga2O3, and device-grade diamond growth. The session will focus on novel device structure design and fabrication technology to achieve high Figure of Merit and gate driving technology for reliable, high-speed switching. Research on the reliability and ruggedness of power devices and modules, which have recently gained increasing attention due to their expanded application in electric vehicles, national defense, and space technologies, will be introduced. Additionally, equipment technology for power device manufacturing will be discussed as an important topic in this session.

• Substrate and epitaxial layer growth of wide bandgap compound semiconductor
• Fabrication process and manufacturing equipment technology for power devices
• Novel device design, device physics, TCAD and circuit simulation and
• Measurement and characterization of power devices and materials
• Device reliability and ruggedness for harsh environment
• Gate driving circuit and technology for robust driving of Power Module
• Materials, novel manufacturing method and multi-physics analysis of Power Module
• Fabrication and Multiphysics modeling technologies for Package, Module fabrication
• Power Electronic System employing wide bandgap power transistor.

The Carbon Neutrality in Semiconductor Industry is a session designed to present diverse research outputs related with carbon neutrality in semiconductor industry. Recognition of ever-growing interests in carbon neutrality in semiconductor industry necessitates high demand for energy efficiency, next-generation etching/deposition process, waste recovery, low GWP material, and life cycle assessment for various processes employed in semiconductor industry and this session can provide an excellent venue to exchange ideas and research works between academia, industry partners, and government officials.

• RE 100/CF 100
• Sustainable etching/deposition process
• Energy efficiency
• Waste recovery
• Low GWP material development
• CO2 capture and utilization
• Power to X
• Life cycle assessment